The present invention relates generally to semiconductor fabrication and, more particularly to the formation of an integrated spacer for gate, source, and drain isolation in a vertical device semiconductor structure.
Integrated circuit fabrication involves creating features into a substrate, generally silicon, which results in various devices such as transistors and capacitors. The fabrication of transistors and capacitors are of particular importance in memory devices that use transistors to transfer charge and capacitors to store charge. Designers, however, are increasingly faced with shrinking circuit sizes. These shrinking sizes result in challenges in designing integrated circuits that require large capacitor size, which takes up a larger area on the circuit and is in conflict with shrinking circuit sizes. Dynamic Random Access Memory (DRAM) devices, in particular, suffer from the aforementioned problem.
Another problem in DRAM design involves the increase in leakage current as transistor devices become smaller. To resolve this problem, deep trench transistors and capacitors are utilized to reduce the amount of substrate surface that is needed to produce a device. Isolation of these devices, however, requires the formation of elements that require extra lithographic steps and thus increases costs. What is needed, therefore, is a memory cell design that provides for good isolation of source and drain contacts from the vertical gate that does not excessively increase the device size.
These above-described and other problems are generally solved or circumvented, and technical advantages are generally achieved, by the present invention.
In a first aspect the present invention provides for a method for forming a spacer in a semiconductor device having a trench for formation of a gate electrode. The device comprises a pad oxide formed adjacent to each side of the trench, and a pad nitride on top of the pad oxide. The method includes depositing a first conductive material onto a gate oxide layer formed within the trench and atop the pad nitride, depositing a second conductive material atop the first conductive material, planarizing the conductive material and the gate electrode layer to a level coplanar with the pad nitride, and removing the pad nitride. The method further includes etching the first conductive material to a predetermined depth within the trench to form a divot, and forming an integrated spacer within the divot.
In another aspect, the present invention provides for a method of forming a memory device having a vertical array transistor whereby a gate electrode is formed within a trench, the device comprising a pad oxide formed adjacent the trench, and having a pad nitride on top of the pad oxide. The method comprises depositing a first conductive material onto a gate oxide layer formed within the trench and atop the pad nitride, depositing a second conductive material having selective etch properties relative the first conductive material onto the first conductive material, the first and second conductive material forming a gate electrode, planarizing the first and second conductive material to a level coplanar with a top surface of the pad nitride, and removing the pad nitride. The method further comprises etching the first conductive material to a predetermined depth within the trench to form a divot, and depositing a liner layer within the divot, whereby a spacer is formed within the divot. The method further includes depositing a second liner layer, depositing an array top oxide on top of the second liner layer, planarizing the array top oxide to a level coplanar to the top of the second liner layer, removing the second liner layer from atop the gate electrode, forming gate conductors atop the gate electrode and the array top oxide, and forming sidewall spacers at each side of the gate conductors.
In other aspects, the present invention provides for integrated circuits and devices formed using the above-described methods.
An advantage of the preferred embodiments of the present invention is that source and drain contacts can be isolated from the vertical gate and the amount of substrate surface needed to produce a device can often be decreased.
Another advantage of the preferred embodiments of the present invention is that an integrated spacer is provided for a vertical array structure, which does not require extra lithographic steps.
A further advantage of a preferred embodiment of the present invention is that a control mechanism is provided that improves control over the etching of divots in the periphery of the gate electrode.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.